Semiconductor apparatus incorporating MOS transistors with reduced narrow channel effect

ABSTRACT

A semiconductor apparatus incorporating MOS transistors with reduced narrow or reverse narrow channel effect and a method for forming the semiconductor apparatus are disclosed. The semiconductor apparatus includes at least a field oxide layer for device isolation formed on a semiconductor substrate, a channel stopper region formed under the field oxide layer, and a MOS transistor of a first conductivity type electrically isolated by the field oxide layer and channel stopper region, in which the MOS transistor includes an impurity region for controlling narrow effect formed in the vicinity of both ends of a channel region in the direction of channel width, and a high concentration impurity region formed having an impurity concentration approximately equal to that of the channel stopper region at the location deeper than the channel stopper region. The MOS transistor can suitably be incorporated into a current mirror circuit, for example, to be included in semiconductor apparatuses such as a constant voltage generation circuit and a voltage detection circuit with improved precision.

BACKGROUND

[0001] 1. Field

[0002] This patent specification relates to a semiconductor apparatusand, more particularly, to such apparatus incorporating MOS transistorswith reduced narrow channel effect and a method for forming thesemiconductor apparatus.

[0003] This document claims priority and contains subject matter relatedto Japanese Patent Application No. 2002-237914, filed with the JapanesePatent Office on Aug. 19, 2002, the entire contents of which are herebyincorporated by reference.

[0004] 2. Discussion of the Background

[0005] In the application of MOS (Metal Oxide Semiconductor) transistorsto semiconductor circuits, it has been known that the narrow channeleffect (or narrow effect) may result for decreased channel widths,caused by seeping out of impurity ions from a channel stopper regionformed under a field oxide layer.

[0006] This narrow channel effect will be described herein below for anNMOS transistor in reference to FIGS. 11A and 11B.

[0007]FIG. 11A plots the threshold voltage V_(th), vertically, as afunction of the channel width W, horizontally, for an N-channel type MOStransistor. In similar manner for the N-type MOS transistor, FIG. 11Bplots the saturation current Id, vertically, as a function of thechannel width W, horizontally, at the applied gate voltage fixed to beapproximately 1.0 volt which is frequently utilized in analoguecircuits.

[0008] There referred to hereinafter are NMOS for N-channel type MOStransistor and PMOS for P-channel type MOS transistor, respectively.

[0009] Referring now to FIG. 11A, the threshold voltage V_(th) increaseswith decreasing channel width, which is indicative of the narrow channeleffect.

[0010] In addition, although the saturation current without the narrowchannel effect is expected to change linearly with channel width W (thedotted straight line shown in FIG. 11B), the actual feature of thechange considerably deviates from the linear relation particularly inthe range of decreased channel width (the solid curved line shown alsoin FIG. 11B), which is considered due to the undue effect from thedecrease in the channel width on threshold voltage caused by the narrowchannel effect.

[0011] This non-linearity may adversely affect on designing MOStransistor circuits, for example.

[0012]FIG. 12 is prepared to illustrate a current mirror circuit, andthe adverse effects on circuit design, which is resulted from the notednon-linearity in the saturation current versus channel width relation,will be described in reference to FIG. 12.

[0013] The current mirror circuit is formed, as generally known, byconnecting two or more transistors so that the current in one node isduplicated in the other. If the sources of two MOS transistors are tiedtogether, and their gates are connected by one of the drains, thecurrent in the first drain is duplicated in the second drain.

[0014] The current mirror circuit can therefore serve to generatecurrent of the same magnitude or the desired current ratio in comparisonwith a reference source current, and widely used in analogue circuitrysuch as, for example, a constant biasing current source, constantcurrent load and current ratio divider.

[0015] As an example, if the MOS transistors, Q1 and Q2, shown in FIG.12, are designed to have the same channel length L and channel widthswith a ratio of 1:10 for Q1 and Q2, the ratio of the resultant currentshas to be I₁:I₂=1:10.

[0016] However, when the MOS transistors used in the decreased channelwidth range in which the narrow channel effect becomes evident as shownin FIG. 11B, the relation between the resultant currents becomesI₁:I₂>1:10, whereby errors in circuit design may arise.

[0017] As an attempt to alleviate such a drawback, the channel width ofthe MOS transistor Q1 might be increased as to be brought into thelinearity region in which the saturation current changes linearly withthe channel width. This method, however, naturally gives rise to theincrease in resultant threshold currents, I₁ and I₂, which isdisadvantageous to semiconductor devices such as, for example, LSI(large-scale integrated circuit) in use for cellular phones, for whichpower consumption as small as possible is desirable.

[0018] In addition, this method also gives rise to a further drawbacksuch as the increase in the transistor size, which is againdisadvantageous to the viewpoint of circuit pattern layout.

[0019] For the reasons indicated above, several methods have beendevised to alleviate the narrow channel effect on MOS transistors.

[0020] As indicated earlier, this effect is considered to be physicallycaused primarily by impurity ions, which are originally included in achannel stopper region to serve to electrically isolate MOS transistorseach other and to seep (or diffuse) out into the channel region in theMOS transistor.

[0021]FIG. 13 is a cross-sectional view along the channel widthdirection illustrating a previously known NMOS transistor.

[0022] Referring to FIG. 13, the NMOS transistor includes at least afield oxide layer 5 for device isolation formed on the surface of aP-type silicon substrate 1.

[0023] The impurities 6 for correcting threshold voltage such as, forexample, boron ions are then introduced into a channel region includedin an active region surrounded by the field oxide layer 5 to therebyform a channel stopper region 9.

[0024] In addition, a gate electrode 15 (which is hereinafter referredto as polysilicon gate) is formed over the channel region formed in theP-type silicon substrate 1 with a gate oxide layer 13 interposed therebetween.

[0025] As shown in FIG. 13, the channel stopper region 9 is formedentering to the channel region.

[0026] Since the impurities forming the channel stopper region 9 have aconcentration higher than the impurities 6 for correcting thresholdvoltage, the impurity concentration increases in the edge portion of thechannel region.

[0027] Such a feature of impurity seeping out from the channel stopperregion 9 into channel region is known to give rise to the increase inthreshold voltage with decreasing channel width, as shown earlier inFIG. 11A, that is, the narrow channel effect.

[0028] Disclosed previously in Japanese Laid-Open Patent Application No.3-64946 is a method of alleviating the narrow channel effect.

[0029] In that method, the acceleration energy for ion implantation intothe channel stopper region is increased to lower further the peaklocation of implanted ions, decrease the impurity concentration in thechannel stopper in the vicinity of field oxide layer, and thereby reducethe impurity seeping out from the channel stopper region into thechannel region.

[0030] In Japanese Laid-Open Patent Application No. 2-277847, a furthermethod is disclosed, in which a silicon nitride layer is provided toform a pattern for defining the region for forming a field oxide layer,and sidewall spacers are then formed on the side faces of the pattern ofthe silicon nitride layer.

[0031] During the impurity introduction into the channel stopper region,these sidewall spacers are utilized so as to allocate a suitabledistance between the region with introduced impurities and a forthcomingchannel region, also to be used as a mask for the implantation of twokinds of ions each having different diffusion coefficients (such as, forexample, arsine and phosphorus ions) as impurities into the channelstopper region such that high punch-through withstand voltages can beretained and that edge portions of active region of the transistor ispredominated by the ions with the smaller diffusion coefficient, tothereby achieving a resultant low impurity concentration.

[0032] Thus, there have been disclosed the methods of lowering the peaklocation of implanted ions and providing sidewall spacers as offsetregions during the impurity introduction into the channel stopper regionand thereby allocating a distance suitable for suppressing thelongitudinal impurity diffusion or seeping out from the channel stopperregion into the active region.

[0033] In these methods, however, the width of resulting offset regionsmay tend to unduly fluctuate owning to several process factors in thecourse of following process steps such as oxide layer etching and heattreatment, thereby giving rise to difficulties in properly controllingthe narrow channel effect.

[0034] In addition, one kind of impurities is often used both channeland channel stopper regions. In such circumstances, if the impurityconcentration is increased to enhance the channel stop effect, theincrease in seeping out into the channel region may be induced so as toresult in the undue enhancement of the narrow channel effect.

[0035] By contrast, if the impurity concentration is decreased tosuppress the narrow channel effect, the channel stop effect may also bereduced.

[0036] Therefore, the range of impurity concentration suitable for bothchannel stop and narrow channel effect is quite limited.

[0037] Furthermore, when the noted seeping out of the impurities in thechannel stopper region into channel region is suppressed excessively,portions entirely deficient of the channel stopper region may arisearound the edge portion of the channel region, as illustrated by the lowconcentration region 63 of FIG. 14.

[0038] In such a case, if the impurity concentration in the lowconcentration region 63 is lower than that in the channel region evenafter including the impurities 6 for correcting threshold voltage, thereverse narrow channel effect (or reverse narrow effect) is caused, inthat the threshold voltage V_(th) decreases with decreasing channelwidth.

[0039] This reverse narrow channel effect is opposite to the narrowchannel effect shown earlier in reference to FIG. 11.

[0040] Referring now to FIGS. 15A and 15B, the reverse narrow channeleffect will be described herein below for an NMOS transistor.

[0041]FIG. 15A plots the threshold voltage V_(th), vertically, as afunction of the channel width W, horizontally, while FIG. 11B plots thesaturation current Id, vertically, as a function of the channel width W,horizontally, at the applied gate voltage fixed to be approximately 1.0volt which is frequently utilized in analogue circuits.

[0042] Referring to FIG. 15A, for the reverse narrow channel effect thethreshold voltage V_(th) decreases with decreasing channel width, whichis in contrast with the case shown earlier for the narrow channel effectin FIG. 11A.

[0043] In addition, although the saturation current without the reversenarrow channel effect is expected to change linearly with channel widthW (the dotted straight line shown in FIG. 15B), the actual feature ofthe change considerably deviates from the linear relation particularlyin the range of decreased channel width (the solid curved line shownalso in FIG. 15B).

[0044] This non-linearity i.e., reverse narrow channel effect mayadversely affect the precision of channel width ratio in a mannersimilar to that caused by the earlier noted narrow channel effect.

[0045] In addition, a further difficulty may arise in that a largenumber of transistors with decreased channel widths are used in asemiconductor apparatus of low power consumption, thereby possiblyresulting in the undue increase in standby currents caused by the smallchannel widths.

[0046] Furthermore, when PMOS and NMOS transistors are both incorporatedinto a semiconductor circuit, the following case may arise. That is, byassuming that a first conductivity type of the transistors (for example,NMOS) are affected by the reverse narrow channel effect, and that theopposite conductivity type of transistors by the narrow effect, thebalance of threshold voltages becomes worsened between these two typesof the transistors, high for the one type and lower for the other.

[0047] This non-linearity, therefore, may give rise to a still furtherdifficulty in designing MOS transistor circuits.

SUMMARY

[0048] Accordingly, it is an object of the present disclosure to providea semiconductor apparatus incorporating MOS transistors with reducednarrow or reverse narrow channel effect and a method for forming theapparatus, having most, if not all, of the advantages and features ofsimilar employed apparatuses and methods, while eliminating many of theaforementioned disadvantages.

[0049] It is another object of the present disclosure to providesemiconductor apparatuses incorporating the MOS transistors disclosedherein, such as a mirror circuit with improved precision, for example,to be included in a constant voltage generation circuit and a voltagedetection circuit.

[0050] The following description is a synopsis of only selected featuresand attributes of the present disclosure. A more complete descriptionthereof is found below in the section entitled “Description of thePreferred Embodiments”.

[0051] A semiconductor apparatus disclosed herein includes at least afield oxide layer for device isolation formed on a semiconductorsubstrate, a channel stopper region formed under the field oxide layer,and a MOS transistor of a first conductivity type electrically isolatedby the field oxide layer and channel stopper region, in which the MOStransistor includes an impurity region for controlling narrow channeleffect formed in the vicinity of both ends of a channel region in thedirection of channel width, and a high concentration impurity regionformed having an impurity concentration approximately equal to that ofthe channel stopper region at the location deeper than the channelstopper region.

[0052] It may be added the noted first conductivity type willhereinafter be referred to either the P or N-type, while a secondconductivity type is opposite to that of the first conductivity type.

[0053] In the MOS transistor, another impurity region for controllingnarrow effect is formed preferably having the same kind, and the sameconcentration, of impurities as those of the impurity region forcontrolling narrow effect, in the region for forming another MOStransistor of a second conductivity type (opposite to that of the firstconductivity type) in the vicinity of both ends of a channel region inthe direction of channel width.

[0054] In addition, the impurities in the impurity region forcontrolling the narrow effect may have the conductivity type opposite tothat of the high concentration impurity region.

[0055] Since the narrow effect controlling impurity region is providedin the region in the vicinity of both ends of the channel region in thedirection of channel width of the MOS transistor, the reverse narrowchannel effect or the narrow channel effect can be controlled bysuitably adjusting the impurity concentration in the narrow effectcontrolling impurity region, and the MOS transistors unaffected eitherby the reverse narrow channel effect or the narrow channel effect can befabricated.

[0056] According to another aspect, a further semiconductor apparatus isprovided including a current mirror circuit which incorporate MOStransistors disclosed herein.

[0057] In addition, a further semiconductor apparatus is providedincluding an analog circuit consisting dividing resistors for dividing avoltage to be measured and supplying a divided voltage, a referencevoltage source for supplying a reference voltage, and an operationalamplifier for comparing the divided voltage with reference voltage, inwhich the operational amplifier includes at least the above notedcurrent mirror circuit.

[0058] Since the MOS transistors disclosed herein is incorporated intothe current mirror circuit and accordingly into the analog circuit, theprecision in power output for these circuits can be improved.

[0059] According to still another aspect, a method for manufacturing thenoted semiconductor apparatus is provided including the steps of

[0060] (A) forming an oxidation resistant coating for defining theregion for forming the field oxide layer;

[0061] (B) implanting ions of a first impurity for controlling reversenarrow channel effect into the semiconductor substrate using theoxidation resistant coating as a mask, as a first implantation process;

[0062] (C) selectively forming a field oxide layer through heattreatment on the surface of the semiconductor substrate; and

[0063] (D) implanting ions of a second impurity from above the fieldoxide layer into the semiconductor substrate for forming a channelstopper region at the location deeper than the first impurity channelstopper region at least in the vicinity of both ends of the channelregion in the direction of channel width of the MOS transistor, as asecond implantation process.

[0064] The MOS transistor disclosed herein can therefore be fabricatedincluding an impurity region for controlling narrow channel effectformed in the vicinity of both ends of a channel region in the directionof channel width, and a high concentration impurity region formed havingan impurity concentration approximately equal to that of the channelstopper region at the location deeper than the channel stopper region.

[0065] In addition, the present method for manufacturing the notedsemiconductor apparatus may alternatively be carried including the stepof,

[0066] prior to the first implantation process (A), forming a wellregion of a first conductivity type and a further well region of asecond conductivity type opposite to that of the first conductivitytype; in which

[0067] the first implantation process (B) is implemented such that theions of the first conductivity type are implanted, as the ions of thefirst impurity, into the well region of the first conductivity type andthe further well region of the second conductivity type; and which

[0068] the second implantation process (D) is implemented with a maskpattern covering the region of the further well region of the secondconductivity type such that the ions of the first conductivity type areimplanted as the ions of the second impurity into the well region of thefirst conductivity type.

[0069] As a result, in the case where both NMOS and PMOS transistors areincluded, a first narrow effect controlling impurity region for the NMOSor PMOS transistor, and another narrow effect controlling impurityregion for the PMOS or NMOS transistor, can be formed simultaneously.Therefore, the number of steps of device production decreases and theproduction costs can be reduced.

[0070] According to another aspect, a further method for manufacturingthe noted semiconductor apparatus is provided including the steps of

[0071] (A) forming an oxidation resistant coating for defining theregion for forming the field oxide layer and subsequently a field oxidelayer selectively through heat treatment on the surface of thesemiconductor substrate,

[0072] (B) forming a mask pattern having openings over the regions forforming a narrow effect controlling impurity region and the channelstopper region, and subsequently implanting ions of a first impurity forcontrolling the reverse narrow channel effect into the semiconductorsubstrate using the mask pattern as a mask, as a first implantationprocess, and

[0073] (C) implanting ions of a second impurity into the semiconductorsubstrate using the same mask pattern for forming a channel stopperregion at the location deeper than the first impurity channel stopperregion at least in the vicinity of both ends of the channel region inthe direction of channel width of the MOS transistor, as a secondimplantation process.

[0074] The noted MOS transistors can therefore be fabricated unaffectedby the reverse narrow channel effect or the narrow channel effect, andproduction costs can be reduced since ion implantation processes forforming the narrow effect controlling impurity region and highconcentration impurity region are carried out using the same mask.

[0075] In addition, during the above noted methods the ions of the firstimpurity used in the first implantation process may have a conductivitytype opposite to that of the second impurity used in the secondimplantation process.

[0076] As a result, the methods for manufacturing a semiconductor devicedisclosed may also be adapted to depletion-mode NMOS transistors byimplanting impurity ions of the conductivity type opposite to that ofions of the channel stopper, whereby the reverse narrow channel effector narrow channel effect can properly be suppressed.

[0077] The present disclosure and features and advantages thereof willbe more readily apparent from the following detailed description andappended claims when taken with drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0078]FIG. 1 is a cross-sectional view in the direction of channel widthillustrating a semiconductor device according to one embodimentdisclosed herein;

[0079]FIGS. 2A through 2C are each cross-sectional views illustratingthe method for manufacturing a semiconductor device during variousstages in the process according to one embodiment disclosed herein;

[0080]FIG. 3A includes a graphical plot of device characteristics of theenhancement-mode NMOS fabricated according to one embodiment disclosedherein, the threshold voltage V_(th), vertically, as a function of thechannel width W, horizontally;

[0081]FIG. 3B includes a graphical plot of the threshold voltage V_(th),vertically, as a function of the channel width W, horizontally, for theenhancement-mode NMOS of FIG. 3A;

[0082]FIGS. 4A through 4C are each cross-sectional views along thechannel width direction illustrating the method for manufacturing adepletion-mode NMOS transistor during various stages in the processaccording to another embodiment disclosed herein;

[0083]FIGS. 5A through 5C are each cross-sectional views along thechannel width direction illustrating the method for manufacturingsemiconductor devices during various stages in the process includingenhancement-mode NMOS and PMOS transistors;

[0084]FIGS. 6A and 6B plot the threshold voltage V_(th), vertically, asa function of the channel width W, horizontally, for the PMOS and NMOStransistors including narrow effect controlling impurity regionsdisclosed herein;

[0085]FIGS. 6C and 6D are prepared for comparison for PMOS and NMOStransistors without the narrow effect controlling impurity regions,plotting the threshold voltage V_(th), vertically, as a function of thechannel width W, horizontally;

[0086]FIGS. 7A and 7B are each cross-sectional views along the channelwidth direction illustrating the portion of the method for manufacturingsemiconductor devices during various stages in the process according tostill another embodiment disclosed herein;

[0087]FIGS. 8A through 8D are each cross-sectional views along thechannel width direction illustrating a further method for manufacturinga semiconductor device during various stages in the process according toanother embodiment disclosed herein;

[0088]FIG. 9 is an electrical schematic diagram illustrating asemiconductor apparatus provided with a constant voltage generationcircuit as an analogue circuit according to another embodiment disclosedherein;

[0089]FIG. 10 is an electrical schematic diagram illustrating a furthersemiconductor apparatus provided with a voltage detection circuit as ananalogue circuit according to another embodiment disclosed herein;

[0090]FIG. 11A plots the threshold voltage V_(th), vertically, as afunction of the channel width W, horizontally, for a known N-channeltype MOS transistor;

[0091]FIG. 11B plots the saturation current Id, vertically, as afunction of the channel width W, horizontally, for the N-channel typeMOS transistor of FIG. 11A;

[0092]FIG. 12 is prepared to illustrate a known current mirror circuit;

[0093]FIG. 13 is a cross-sectional view along the channel widthdirection illustrating a known NMOS transistor;

[0094]FIG. 14 is a cross-sectional view along the channel widthdirection illustrating a known NMOS transistor in which the seeping outof the impurities in the channel stopper region into channel region issuppressed excessively; and

[0095]FIGS. 15A and 15B are prepared to illustrate the reverse narrowchannel effect plotting the threshold voltage V_(th) versus channelwidth W relation and the saturation current Id versus channel width Wrelation, respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0096] In the detailed description which follows, specific embodimentsof semiconductor apparatus are described, in which MOS transistorsincluded therein are formed with reduced narrow or reverse narrowchannel effect to suitably be incorporated into a current mirror circuitwith improved precision. It is understood, however, that the presentdisclosure is not limited to these embodiments. For example, the use ofthe MOS transistors disclosed herein may also be adaptable to any formof electronic circuits and systems. Other embodiments will be apparentto those skilled in the art upon reading the following description.

[0097]FIG. 1 is a cross-sectional view in the direction of channel widthillustrating an enhancement-mode NMOS transistor as the semiconductordevice according to one embodiment disclosed herein.

[0098] Referring to FIG. 1, a P-type drain well region 3 is formed in aP-type semiconductor silicon substrate 1 and a field oxide layer 5 fordevice isolation is formed on the substrate 1.

[0099] Subsequently, P-type impurities such as, for example, boron ionsare introduced as the impurities 6 for correcting threshold voltage intoa channel region included in an active region surrounded by the fieldoxide layer 5.

[0100] In addition, further P-type impurities such as, for example,boron ions are introduced to form a narrow effect controlling impurityregion 7 into the region in the vicinity of both ends of the channelregion in the direction of channel width.

[0101] A channel stopper region 9 is formed under the field oxide layer5 by introducing boron ions, for example. In the region under the narroweffect controlling impurity region 7, a high concentration impurityregion 11 is formed spatially separated from the channel region byintroducing boron ions, for example.

[0102] The channel stopper region 9 has the approximately same impurityconcentration as the high concentration impurity region 11, while theimpurity concentration of channel stopper region 9 and highconcentration impurity region 11 is larger than the narrow effectcontrolling impurity region 7.

[0103] In addition, a polysilicon gate 15 is formed over the channelregion in the P-well region 3 with a gate oxide layer 13 interposedthere between.

[0104] Since the channel region in the present NMOS transistor is formedspatially separated from the channel stopper region 9 and highconcentration impurity region 11, seeping out of impurity ions to thechannel region from the channel stopper region 9 and high concentrationimpurity region 11 is alleviated, whereby the narrow channel effect canbe prevented.

[0105] Furthermore, since the narrow effect controlling impurity region7 is provided in the region in the vicinity of both ends of the channelregion in the direction of channel width of the MOS transistor, eitherthe reverse narrow channel effect or the narrow effect can be controlledby suitably adjusting the impurity concentration in the narrow effectcontrolling impurity region.

[0106] Still further, the NMOS unaffected either by the reverse narrowchannel effect or the narrow channel effect can be fabricated.

[0107]FIGS. 2A through 2C are each cross-sectional views along thechannel width direction illustrating the method for manufacturing asemiconductor device during various stages in the process and FIG. 2Cillustrates the fabricated enhancement-mode NMOS transistor as thesemiconductor device according to one embodiment disclosed herein.

[0108] (1) Following the formation of a P-well region 3 in a P-typesilicon substrate 1, a silicon oxide layer 17 is formed over thestructure. In the present embodiment, a P-type silicon substrate havinga resistivity of 20 Ω-cm and a P-type impurity concentration ofapproximately 6×10¹⁴ cm⁻³ is used as the silicon substrate 1, and theP-well region 3 is formed by introducing P-type impurities of a peakconcentration of approximately 1×10¹⁷ cm⁻³ into the P-type siliconsubstrate 1.

[0109] A retro-graded well may alternatively be formed as the P-wellregion 3, which has the impurity concentration higher in the inside of,while lower on the surface of the substrate.

[0110] Since the impurity concentration in the vicinity of the substratesurface in this case becomes lower than previously known well region,the reverse narrow channel effect tends to form with more ease. As aresult, the effect of suppressing the reverse narrow channel effectincreases.

[0111] Subsequently, a silicon nitride layer is formed over the siliconoxide layer 17. The silicon nitride layer is then subjected topatterning steps to form an oxidation resistant coating 19. Using theoxidation resistant coating 19 as a mask, P-type impurities such as, forexample, boron ions (B⁺) are implanted using ion implantation techniques(FIG. 2A). This ion implantation step constitutes the first ionimplantation step in the semiconductor device fabrication methoddisclosed herein.

[0112] The conditions of ion implantation during the above noted process(1) are adjusted as an acceleration energy of 15 keV and a dose of1.2×10¹³ cm⁻² so as to attain an implanted ion concentration one ordersmaller than that by the previous method of implanting collectivelyprior to field oxidation.

[0113] This is on the ground that the ion implantation herein is carriedout for suppressing the reverse narrow channel effect rather thanforming the channel stopper. Accordingly, the dose for the implantationis preferably adjusted approximately equal to, or smaller than 1.2×10¹³cm⁻².

[0114] (2) After forming a field oxide layer 5 by the LOCOS (localoxidation of silicon) method on the surface of P-type silicon substrate1, the oxidation resistant coating 19 is removed.

[0115] The boron ions implanted during the process (1) are thereforedistributed in boron implanted region 21 (the region designated by themark ‘X’) under the field oxide layer 5.

[0116] Subsequently, boron ions (B⁺) are implanted under the conditionsof an acceleration energy of 180 keV and a dose of 1×10¹³ cm⁻².

[0117] The thus implanted boron ions are distributed in another boronimplanted region 23 (the region designated by the mark ‘◯’). The depthof this region is determined by the thickness of overlying layers, thatis, relatively shallow under the field oxide layer 5, while deeper underthe silicon oxide layer 17 (FIG. 2B).

[0118] This ion implantation step constitutes the second ionimplantation step in the semiconductor device fabrication method.

[0119] In addition, the impurity introduction for correcting thresholdvoltage into a channel region can be carried out under conditionsproperly determined depending on desired values of threshold voltage.This is exemplified by the ion implantation of P-type impurities suchas, for example, boron ions under the conditions of an accelerationenergy of 10 keV and a dose of approximately 3×10¹² cm⁻².

[0120] (3) Following the removal of the silicon oxide layer 17, a gateoxide layer 13 is formed to a thickness of approximately 7 nm on thesurface of the channel region in the P-well region 3.

[0121] Subsequently, a polysilicon layer is formed over the structureand then subjected to patterning steps to form a polysilicon gate 15.

[0122] Furthermore, a source and drain regions (not shown) of MOStransistor are formed by the well known process, and subjected to heattreatment steps for activating the implanted ions.

[0123] As a result, there provided in the P-well region 3 are a channelstopper region 9 which is formed of the boron implanted regions 21, 23under the field oxide layer 5, a narrow effect controlling impurityregion 7 formed of the boron implanted region 21 in the region in thevicinity of both ends of the channel region in the direction of channelwidth, and a high concentration impurity region 11 formed of the boronimplanted region 23 in the region under the narrow effect controllingimpurity region 7 spatially separated from the channel region (FIG. 2C).

[0124] In the present embodiment, therefore, the channel region, channelstopper region 9, and high concentration impurity region 11 are formedspatially separated from each other. The NMOS transistor can thereforebe formed including the narrow effect controlling impurity region 7provided in the region in the vicinity of both ends of the channelregion in the direction of channel width.

[0125] As a result, either the reverse narrow channel effect or thenarrow channel effect is properly controlled, and the enhancement-modeNMOS can be fabricated unaffected by the reverse narrow channel effector the narrow channel effect.

[0126] It may be added that during the process (2) for implanting boronions for forming the boron implanted region 23 described earlier inreference to FIG. 2B, a mask pattern may be provided on the siliconoxide layer 17 so as to cover the channel region. Since no boron ion isimplanted into the region under the channel region in this case, thestructure shown in FIG. 1 can be formed.

[0127] As a result, by the impurity concentration in the region underthe channel region thereby retained relatively low, the back bias effectcan be suppressed, and this makes the countermeasures for low voltagecapability feasible with more ease.

[0128]FIGS. 3A and 3B each include graphical plots of devicecharacteristics of the enhancement-mode NMOS fabricated according to oneembodiment disclosed herein, in which there plotted are the thresholdvoltage V_(th), vertically, as a function of the channel width W,horizontally, in FIG. 3A; and the saturation current I_(d) as a functionof W at a fixed applied voltage of approximately 1 volt in FIG. 3B.

[0129] As illustrated in FIG. 3A, the threshold voltage remains constanteven decreased channel width W by suitably suppressing the reversenarrow channel effect or the narrow effect.

[0130] The linear relation of the saturation current versus channelwidth W is therefore provided, and this makes the circuit design of highprecision analogue circuits feasible with more ease.

[0131]FIGS. 4A through 4C are each cross-sectional views along thechannel width direction illustrating the method for manufacturing asemiconductor device during various stages in the process and FIG. 4Cillustrates the fabricated depletion-mode NMOS transistor as thesemiconductor device according to another embodiment disclosed herein.

[0132] In addition, the components in the drawings similar to those inFIGS. 2A through 2C are shown with identical numerical representationsand detailed description thereof is herein abbreviated.

[0133] Referring now to FIG. 4C, a P-type drain well region 3 is formedin a P-type silicon substrate 1 and a field oxide layer 5 for deviceisolation is formed on the substrate 1.

[0134] Subsequently, the impurities for correcting threshold voltage(not shown) such as, for example, phosphorus ions are introduced in thevicinity of the surface region of P-well region 3 into a channel regionincluded in an active region surrounded by the field oxide layer 5.

[0135] In addition, further P-type impurities such as, for example,phosphorus ions are introduced to form a narrow effect controllingimpurity region 25 into the region in the vicinity of both ends of thechannel region in the direction of channel width.

[0136] A channel stopper region 9 is formed under the field oxide layer5 by introducing boron ions, for example.

[0137] In the region under the channel region and narrow effectcontrolling impurity region 25, a high concentration impurity region 11is formed spatially separated from the channel region.

[0138] The channel stopper region 9 and the high concentration impurityregion 11 each have an impurity concentration higher than the narroweffect controlling impurity region 25.

[0139] In addition, a polysilicon gate 15 is formed over the channelregion in the P-well region 3 with a gate oxide layer 13 interposedthere between.

[0140] Since the impurity ions introduced into the channel region are ofN-type, seeping out of P-type impurity ions has a relatively largeeffect on the narrow channel effect can be prevented.

[0141] The channel region is formed spatially separated from the channelstopper region 9 and high concentration impurity region 11 in thepresent NMOS transistor. Therefore, the seeping out of impurity ions tothe channel region from the channel stopper region 9 and highconcentration impurity region 11 is alleviated, whereby the undue affectto the narrow channel effect can be prevented.

[0142] Furthermore, the narrow effect controlling impurity region 25with the conductivity type opposite to that of the channel stopperregion 9 and high concentration impurity region 11 is provided in theregion in the vicinity of both ends of the channel region in thedirection of channel width of the MOS transistor.

[0143] Therefore, either the reverse narrow channel effect or the narrowchannel effect can be controlled by suitably adjusting the impurityconcentration in the narrow effect controlling impurity region, wherebythe depletion-mode NMOS unaffected by the reverse narrow channel effector the narrow channel effect can be fabricated.

[0144] Referring now to FIGS. 4A through 4C, the method formanufacturing the NMOS transistor will be described according to anotherembodiment disclosed herein.

[0145] (1) Following the formation of a P-well region 3 in a P-typesilicon substrate 1, a silicon oxide layer 17 is formed over thestructure.

[0146] A silicon nitride layer is then formed over the silicon oxidelayer 17. The silicon nitride layer is subsequently subjected topatterning steps to form an oxidation resistant coating 19.

[0147] P-type impurities such as, for example, phosphorus ions (P⁺) areimplanted using ion implantation techniques under the conditions of anacceleration energy of 70 keV and a dose of ranging from 1×10¹² cm⁻² to5×10¹² cm⁻² (FIG. 4A). This ion implantation step constitutes the firstion implantation step in the semiconductor device fabrication methoddisclosed herein.

[0148] Since the ion implantation herein is carried out for suppressingthe reverse narrow channel effect, the dose for the implantation ispreferably adjusted approximately equal to, or smaller than 2×10¹³ cm⁻².

[0149] (2) After forming a field oxide layer 5 by the LOCOS (localoxidation of silicon) method on the surface of P-type silicon substrate1, the oxidation resistant coating 19 is removed.

[0150] The phosphorus ions implanted during the process (1) aretherefore distributed in phosphorus implanted region 27 (the regiondesignated by the mark ‘Δ’) under the field oxide layer 5.

[0151] Subsequently, boron ions (B⁺) are implanted under the conditionsof an acceleration energy of 180 keV and a dose of 1×10¹³ cm⁻² to form aboron implanted region 23 (the region designated by the mark ‘◯’) asshown in FIG. 4B.

[0152] In addition, for introducing the impurities for correctingthreshold voltage into a channel region, the conditions for theintroduction can properly be determined corresponding to desired valuesof threshold voltage, which are exemplified by the ion implantation ofN-type impurities such as, for example, phosphorus ions under theconditions of an acceleration energy of 70 keV and a dose ofapproximately 5×10¹² cm⁻².

[0153] (3) Following the removal of the silicon oxide layer 17, a gateoxide layer 13 is formed to a thickness of approximately 7 nm on thesurface of the channel region in the P-well region 3.

[0154] Subsequently, a polysilicon layer is formed over the structureand then subjected to patterning steps to form a polysilicon gate 15.

[0155] Furthermore, a source and drain regions (not shown) of MOStransistor are formed by the well known process, and subjected to heattreatment steps for activating the implanted ions.

[0156] As a result, there provided in the P-well region 3 are a narroweffect controlling impurity region 25 which is formed of the phosphorusimplanted region 27 in the region in the vicinity of both ends of thechannel region in the direction of channel width, and a highconcentration impurity region 11 formed of the boron implanted region 23in the region under the narrow effect controlling impurity region 25spatially separated from the channel region.

[0157] In addition, although the phosphorus implanted region 27 isformed under the field oxide layer 5 through the process (1) and theboron implanted region 23 through the process (2), the boron ionconcentration is higher than phosphorus ions, whereby P-type channelstopper region 9 can be formed (FIG. 4C).

[0158] In the present embodiment, therefore, since the channel region,channel stopper region 9, and high concentration impurity region 11 areformed spatially separated from each other, the NMOS transistor can beformed including the narrow effect controlling impurity region 25provided in the region in the vicinity of both ends of the channelregion in the direction of channel width.

[0159] Therefore, either the reverse narrow channel effect or the narrowchannel effect is properly controlled, and the depletion-mode NMOS canbe fabricated unaffected by the reverse narrow channel effect or thenarrow channel effect.

[0160]FIGS. 5A through 5C are each cross-sectional views along thechannel width direction illustrating the method for manufacturingsemiconductor devices during various stages in the process and FIG. 5Cillustrates the fabricated enhancement-mode NMOS and PMOS transistors asthe semiconductor devices according to still another embodimentdisclosed herein.

[0161] In addition, the components in the drawings similar to those inFIGS. 2A through 2C are shown with identical numerical representationsand detailed description thereof is herein abbreviated.

[0162] A P-well region 3 and an N-well region 29 are formed in a P-typesilicon substrate 1 and a field oxide layer 5 for device isolation isformed on the substrate 1.

[0163] Subsequently, there formed in the P-well region 3 are a P-typenarrow effect controlling impurity region 7 which is formed in theregion in the vicinity of both ends of the channel region in thedirection of channel width, a channel stopper region 9 which is formedunder the field oxide layer 5, and a P-type high concentration impurityregion 11 which is formed under the regions of the channel and narroweffect controlling impurity region 7.

[0164] In the N-well region 29, a narrow effect controlling impurityregion 31 is formed by introducing P-type impurities such as, forexample, boron ions into the regions such as in the vicinity of bothends of the channel region in the direction of channel width and underthe field oxide layer 5.

[0165] The boron ions into the narrow effect controlling impurity region31 are introduced simultaneously with those for forming the narroweffect controlling impurity region 7. The channel stopper region 9 andthe high concentration impurity region 11 each have an impurityconcentration higher than the narrow effect controlling impurity region25.

[0166] The thus formed narrow effect controlling impurity region 31constitutes the second narrow effect controlling impurity region in thesemiconductor device disclosed herein.

[0167] In addition, polysilicon gates 15, 15 are formed over therespective channel regions in the P-well region 3 and N-well region 29with gate oxide layers 13, 13 interposed there between.

[0168] In the present NMOS formed in the P-well region 3, in a similarmanner to that for the NMOS previously described in reference to FIG.2C, the channel region, channel stopper region 9, and high concentrationimpurity region 11 are formed spatially separated from each other, andnarrow effect controlling impurity region 7 is formed in the region inthe vicinity of both ends of the channel region in the direction ofchannel width.

[0169] Therefore, either the reverse narrow channel effect or the narrowchannel effect is properly controlled, and the NMOS can be fabricatedunaffected by the reverse narrow channel effect or the narrow channeleffect.

[0170] Furthermore, the PMOS formed in the N-well region 29 is providedwith a narrow effect controlling impurity region 31 in the vicinity ofboth ends of the channel region in the direction of channel width.

[0171] The reverse narrow channel effect or the narrow channel effect istherefore properly controlled, and the PMOS can be fabricated unaffectedby the reverse narrow channel effect or the narrow effect.

[0172] Referring now to FIGS. 5A through 5C, the method formanufacturing the NMOS and PMOS transistors will be described accordingto another embodiment disclosed herein.

[0173] (1) Following the formation of an N-well region 29 and P-wellregion 3 in a P-type silicon substrate 1, a silicon oxide layer 17 isformed over the structure.

[0174] In the present embodiment, the N-well region 29 is formed havingN-type impurities of a peak concentration of approximately 1×10¹⁷ cm⁻³.In addition, retro-grade wells may alternatively be formed as the P-wellregion 3 and N-well region 29.

[0175] Since the impurity concentration in the vicinity of the substratesurface in this case becomes lower than previously known well region,the reverse narrow channel effect tends to form with more ease. As aresult, the effect of suppressing the reverse narrow channel effectincreases.

[0176] Subsequently, silicon nitride layers 19, 19 are formed over thesilicon oxide layer 17. The silicon nitride layers are then subjected topatterning steps to form oxidation resistant coatings 19, 19. Using theoxidation resistant coatings 19, 19 as masks, P-type impurities such as,for example, boron ions (B⁺) are implanted onto the entire structure

[0177] under the conditions of an acceleration energy of 15 keV and adose of approximately 1.2×10¹³ cm⁻².

[0178] This ion implantation step constitutes the first ion implantationstep in the semiconductor device fabrication method disclosed herein.

[0179] Since the ion implantation herein is carried out for suppressingthe reverse narrow channel effect rather than forming the channelstopper, the dose for the implantation is preferably adjustedapproximately equal to, or smaller than 2×10¹³ cm⁻².

[0180] (2) Following the formation of a field oxide layer 5 by the LOCOSmethod on the surface of P-type silicon substrate 1, the oxidationresistant coatings 19, 19 are removed.

[0181] The boron ions implanted during the process (1) are thereforedistributed in boron implanted region 21 (the region designated by themark ‘X’) under the field oxide layer 5.

[0182] Subsequently, a photoresist pattern 33 is formed to cover theN-well region 29 using well known photolithographic techniques, andboron ions (B⁺) are implanted using the photoresist pattern 33 as a maskunder the conditions of an acceleration energy of 180 keV and a dose of1×10¹³ cm⁻² to form a boron implanted region 23 (the region designatedby the mark ‘◯’), thereby for a boron implanted region be formed in theP-well region 3 (FIG. 5B).

[0183] This ion implantation step constitutes the second ionimplantation step in the semiconductor device fabrication methoddisclosed herein.

[0184] In case of impurity introduction into the channel region in theP-well region 3 for correcting threshold voltage of the NMOS transistorcan be carried out under the conditions properly determined depending ondesired values of threshold voltage. This is exemplified by the ionimplantation of P-type impurities such as, for example, boron ions underthe conditions of an acceleration energy of 10 keV and a dose ofapproximately 3×10¹² cm⁻².

[0185] Similarly, the impurity introduction for correcting thresholdvoltage of the PMOS transistor into the channel region in the N-wellregion 29 can be carried out under conditions properly determineddepending on desired values of threshold voltage, such as, for example,an acceleration energy of 10 keV and a dose of approximately 3×10¹² cm⁻²for boron ion implantation, and an acceleration energy of 150 keV and adose of approximately 2×10¹² cm⁻² for phosphorus ion implantation.

[0186] (3) Following the removal of the silicon oxide layer 17, gateoxide layers 13, 13 are formed. A polysilicon layer is then formed overthe structure and then subjected to patterning steps to form polysilicongates 15, 15.

[0187] Furthermore, source and drain regions (not shown) of the MOStransistors are formed by the well known process, and subjected to heattreatment steps for activating the implanted ions.

[0188] As a result, there provided in the P-well region 3 are a channelstopper region 9 which is formed of boron implanted regions 21, 23, anarrow effect controlling impurity region 7 which is formed of the boronimplanted region 7 in the region in the vicinity of both ends of thechannel region in the direction of channel width, and a highconcentration impurity region 11 formed of the boron implanted region 23in the regions under the channel region and the narrow effectcontrolling impurity region 7 spatially separated from the channelregion.

[0189] In addition, a narrow effect controlling impurity region 31 isformed under the regions such as in the vicinity of both ends of thechannel region in the direction of channel width and the field oxidelayer 5 (FIG. 5C).

[0190] In the present embodiment, therefore, P-type impurities forforming a narrow effect controlling impurity region 7 for the NMOStransistor and a further narrow effect controlling impurity region 31for the PMOS transistor, can be formed simultaneously using theoxidation resistant coatings 19, 19 as the masks for defining respectiveregions.

[0191] Therefore, the number of steps of device production decrees andthe production costs can be reduced.

[0192] In the N-well region 29 in the present embodiment, N-typeimpurities under the field oxide layer 5 are utilized for forming theN-well region 29 and the channel stopper region for the PMOS transistor.Therefore, proper care has to be directed to the balance inconcentration between N-type impurities and those in the channel stopperregion for the PMOS transistor in the region under the field oxide layer5.

[0193] That is, for the effective concentration of N-type impurities, itis necessary to retain the magnitude thereof sufficient for functioningas the channel stopper region for the PMOS transistor formed in theN-well region 29, while to control the level thereof to be suitable forachieving proper narrow channel effect. The concentration of P-typeimpurities in the narrow effect controlling impurity region 31 isadjusted preferably equal to, or smaller than 2×10¹³ cm¹².

[0194] The device characteristics of several MOS transistors are shownin FIGS. 6A through 6D, each plot the threshold voltage V_(th),vertically, as a function of the channel width W, horizontally.

[0195]FIGS. 6A and 6B are prepared for the PMOS and NMOS transistorsfabricated as above including narrow effect controlling impurity regionsdisclosed herein, respectively; while FIGS. 6C and 6D are prepared forcomparison for PMOS and NMOS transistors without the narrow effectcontrolling impurity regions, respectively.

[0196] In addition, the channel width is adjusted to be 25 am for therespective transistors.

[0197] It is clearly shown in FIGS. 6C and 6D that the narrow channeleffect is quite evident for the PMOS and NMOS transistors without thenarrow effect controlling impurity regions, respectively, while thenarrow channel effect is considerably improved for the PMOS and NMOStransistors fabricated as above including narrow effect controllingimpurity regions as shown in FIGS. 6A and 6B, respectively.

[0198]FIGS. 7A and 7B are each cross-sectional views along the channelwidth direction illustrating the portion of the method for manufacturingsemiconductor devices during various stages in the process.

[0199] The components in the drawings similar to those in FIGS. 5Athrough 5C are shown with identical numerical representations anddetailed description thereof is herein abbreviated.

[0200] (1-1) Following the formation of an N-well region 29 and P-wellregion 3 in a P-type silicon substrate 1, a silicon oxide layer 17 isformed over the structure. Subsequently, silicon nitride layers areformed over the silicon oxide layer 17.

[0201] A photoresist pattern 35 is then formed to cover the N-wellregion 29 using well known photolithographic techniques, and P-typeimpurities such as, for example, boron ions (B⁺) are implanted using thephotoresist pattern 35 as a mask under the conditions of an accelerationenergy of 15 keV and a dose of 1.5×10¹³ cm⁻² to thereby form a boronimplanted region 21 (the region designated by the mark ‘X’) as shown inFIG. 7A.

[0202] (1-2) Following the removal of the photoresist pattern 35, afurther photoresist pattern 37 is formed to cover the P-well region 3using well known photolithographic techniques.

[0203] P-type impurities such as, for example, boron ions (B⁺) are thenimplanted into the N-well region 29 using the photoresist pattern 37 asa mask under the conditions of an acceleration energy of 15 keV and adose of 1.5×10¹³ cm⁻² to thereby form a boron implanted region 39 (theregion designated by the mark ‘□’) as shown in FIG. 7B.

[0204] Subsequently, a field oxide layer 5 is formed by the process (2)described earlier in reference to FIG. 5B.

[0205] In addition, there formed by the process (3) described earlier inreference to FIG. 5C are a narrow effect controlling impurity region 7,channel stopper region 9, high concentration impurity region 11, gateoxide layer 13, polysilicon gate 15 and narrow effect controllingimpurity regions 31.

[0206] The narrow effect controlling impurity regions 31 is formed ofthe boron implanted region 39.

[0207] In the present embodiment, therefore, the care directed earlierto the balance in concentration may not be necessary between the twomutually opposing conductivity types during the ion implantationprocesses, one the process (1-1) for forming the narrow effectcontrolling impurity region 7 and the process (1-1) for forming thenarrow effect controlling impurity region 7, and the other the process(1-2) for forming the narrow effect controlling impurity regions 31.

[0208] Therefore, the range of control can increase for the narrowchannel effect.

[0209]FIGS. 8A through 8D are each cross-sectional views along thechannel width direction illustrating a further method for manufacturinga semiconductor device during various stages in the process and FIG. 8Dillustrates the fabricated enhancement-mode NMOS transistor as thesemiconductor device according to another embodiment disclosed herein.

[0210] In addition, the components in the drawings similar to those inFIGS. 2A through 2C are shown with identical numerical representationsand detailed description thereof is herein abbreviated.

[0211] (1) Following the formation of a P-well region 3 in a P-typesilicon substrate 1, a silicon oxide layer 17, an oxidation resistantcoating, and a field oxide layer 5 by the LOCOS method are formed inthat order.

[0212] It is noted that ion implantation has not been made for forming anarrow effect controlling impurity region 7 (FIG. 8A).

[0213] (2) A photoresist pattern is formed (not shown) having openingsover several regions such as one for forming a narrow effect controllingimpurity region and the other for a channel stopper region.

[0214] By ion implantation techniques using the photoresist pattern as amask, P-type impurities such as, for example, boron ions (B⁺) areimplanted under the conditions of an acceleration energy of 50 keV and adose of 1.2×10¹³ cm⁻².

[0215] The thus implanted boron ions are distributed in a boronimplanted region 21 a (the region designated by the mark ‘X’). The depthof this region is determined by the thickness of overlying the fieldoxide layer 5 and silicon oxide layer 17, formed over the P-well region3.

[0216] That is, no boron ion is implanted into the P-well region towardthe middle of the field oxide layer 5, some boron ions into the regionrelatively shallow under the field oxide layer 5, while relatively deepunder the silicon oxide layer 17 (FIG. 8B).

[0217] This ion implantation step constitutes the first ion implantationstep in the semiconductor device fabrication method.

[0218] Using the same photoresist pattern as a further mask, boron ions(B⁺) are implanted under the conditions of, for example, an accelerationenergy of 180 keV and a dose of 1×10¹³ cm⁻².

[0219] The boron ions implanted during the process are distributed in aboron implanted region 23 (the region designated by the mark ‘◯’). Thedepth of this region is deeper than the region 21 a (FIG. 8C).

[0220] This ion implantation step constitutes the second ionimplantation step in the semiconductor device fabrication method.

[0221] In case of impurity introduction into the channel region in theP-well region 3 for correcting threshold voltage of the NMOS transistorcan be carried out under the conditions properly determined depending ondesired values of threshold voltage. This is exemplified by the ionimplantation of P-type impurities such as, for example, boron ions underthe conditions of an acceleration energy of 10 keV and a dose ofapproximately 3×10 cm⁻².

[0222] (3) Following the removal of the silicon oxide layer 17, gateoxide layers 13 is formed to a thickness of approximately 7 nm.

[0223] A polysilicon layer is then formed over the structure and thensubjected to patterning steps to form a polysilicon gate 15.

[0224] Furthermore, source and drain regions (not shown) of a MOStransistor are formed by the well known process, and subjected to heattreatment steps for activating the implanted ions.

[0225] As a result, there provided in the P-well region 3 are a narroweffect controlling impurity region 7 a is formed, out of the boronimplanted region 21 a, under the regions such as in the vicinity of bothends of the channel region in the direction of channel width and thefield oxide layer 5, a high concentration impurity region 11 formed ofthe boron implanted region 23 in the regions under the narrow effectcontrolling impurity region 7 a spatially separated from the channelregion, and a channel stopper region 9 which is formed of boronimplanted region 23 (FIG. 8D).

[0226] In the present embodiment, therefore, since the channel region,channel stopper region 9, and high concentration impurity region 11 areformed spatially separated from each other, the NMOS transistor can beformed including the narrow effect controlling impurity region 7 aprovided in the region in the vicinity of both ends of the channelregion in the direction of channel width.

[0227] Therefore, either the reverse narrow channel effect or the narrowchannel effect is properly controlled, and the enhancement-mode NMOS canbe fabricated unaffected by the reverse narrow channel effect or thenarrow channel effect.

[0228] Furthermore, the ion implantation process (2) for forming thenarrow effect controlling impurity region 7 a and the further ionimplantation process (3) for forming the channel stopper region 9 andhigh concentration impurity region 11 are carried out using the samephotoresist pattern as the mask, whereby production costs can bereduced.

[0229] Although the method for manufacturing a semiconductor deviceaccording to the present embodiment has been adapted to the fabricationof enhancement-mode NMOS transistors, it is not intended to be limiting.

[0230] For example, the present method may also be adapted todepletion-mode NMOS transistors by implanting N-type impurities in placeof the aforementioned P-type ions in the ion implantation process (2).

[0231] In addition, although the method has been described on the P-wellregion 3 of the NMOS transistor in the present embodiment to include thenarrow effect controlling impurity region 7, channel stopper region 9and the high concentration impurity region 11, it is not intended to belimiting.

[0232] For example, the narrow effect controlling impurity region,channel stopper region and high concentration impurity region may beformed in the N-well region of PMOS transistor.

[0233] In the method for fabricating semiconductor devices provided withPMOS and NMOS transistors, in particular, the optimization of thereverse narrow channel effect and narrow channel effect becomes feasiblewith high precision through adapting the present method to both PMOS andNMOS transistors.

[0234] Furthermore, although the field oxide layer 5 is formed by theLOCOS method in the embodiments disclosed herein in the method formanufacturing semiconductor devices,

[0235] the field oxide layer 5 may also be formed alternatively by othermethod such as, for example, poly-buffered LOCOS method.

[0236] In the present case, the pertinent layers for the transistors maybe provided in the aforementioned process (1) or (1-1). That is,following the formation of the silicon oxide layer 17, the polysiliconlayer is formed thereon to a thickness ranging from 20 to 50 nm, and theoxidation resistant coating of silicon nitride layer is formed furtherthereon.

[0237] It may be added that the description on the poly-buffered LOCOSmethod is found also in Japanese Laid-Open Patent Application No.9-45677.

[0238] The MOS transistors disclosed herein can suitably be adapted tosemiconductor apparatus such as, for example, the current mirror circuitas illustrated in FIG. 12.

[0239] As described earlier, the reverse narrow channel effect andnarrow channel effect are properly controlled in the MOS transistorsdisclosed herein. By incorporating the MOS transistors into the currentmirror circuit, therefore, the precision in power output increases.

[0240]FIG. 9 is an electrical schematic diagram illustrating asemiconductor apparatus provided with a constant voltage generationcircuit as an analogue circuit according to another embodiment disclosedherein.

[0241] Referring to FIG. 9, a constant voltage generation circuit 45 isdesigned to stably supply the source power output from a direct currentsource 41 to a load 43.

[0242] The constant voltage generation circuit 45 is provided with aninput terminal (V_(bat)) 47 to which the direct current source 41 isconnected, a standard voltage generation circuit (V_(ref)) 49 as areference voltage source, an operational amplifier 51, a P-channel typeMOS transistor (or PMOS) 53 to constitute an output driver, dividingresistors R1 and R2, and an output terminal (V_(out)) 55.

[0243] In the constant voltage generation circuit 45, its outputterminal is connected to a gate electrode of the PMOS 53, the referencevoltage V_(ref) from the reference voltage source is applied to theinverting input terminal of operational amplifier 51; the voltage, whichis obtained by diving V_(out) by means of dividing resistors R1 and R2,is applied to the noninverting input terminal of operational amplifier51; and the divided voltage by the dividing resistors, R1 and R2, isthen adjusted to be equal to the reference voltage V_(ref).

[0244] Also in the constant voltage generation circuit 45, a currentmirror circuit is provided in the operational amplifier 51 incorporatingthe MOS transistors disclosed herein.

[0245] By incorporating the MOS transistors as described above, theprecision in power output from the current mirror circuit is improved,whereby the accuracy in comparison capability of the function of theoperational amplifier 51 and accordingly the precision in power outputof constant voltage generation circuit 45 can be increased.

[0246]FIG. 10 is an electrical schematic diagram illustrating a furthersemiconductor apparatus provided with a voltage detection circuit as ananalogue circuit according to another embodiment disclosed herein.

[0247] Referring to FIG. 10, in the voltage detection circuit 57including an operational amplifier 51, a standard voltage generationcircuit 49 is connected to the inverting input terminal of theoperational amplifier 51 to which the reference voltage V_(ref) isapplied.

[0248] The voltage, which is input from a certain terminal to besubjected presently to voltage measurement, is divided by dividingresistors, R1 and R2, and subsequently input to the noninverting inputterminal of operational amplifier 51. The output voltage from theoperational amplifier 51 is forwarded to the exterior by way of anoutput terminal (V_(out)) 61.

[0249] This voltage detection circuit 57 is designed to operate asfollows.

[0250] If the voltage at the terminal to be presently measured isrelatively high and accordingly the voltage divided by dividingresistors, R1 and R2, is higher than V_(REF), the output of theoperational amplifier 51 becomes high ‘H’; while this output changes tolow ‘L’, when the voltage at the terminal decreases and accordingly thevoltage divided by dividing resistors becomes lower than V_(REF), theoutput of the operational amplifier 51.

[0251] In the voltage detection circuit 57, a further current mirrorcircuit is provided in the operational amplifier 51 incorporating theMOS transistors disclosed herein.

[0252] By including the MOS transistors as described above, theprecision in power output from the current mirror circuit is improved,whereby the accuracy in comparison capability of the function of theoperational amplifier 51 and accordingly the precision in the output ofvoltage detection circuit 57 can increase.

[0253] Although the MOS transistors disclosed herein have been discernedas incorporated into the semiconductor apparatus such as the constantvoltage generation circuit and voltage detection circuit, the presentdisclosure is not limited to above embodiments, but may also beadaptable to other semiconductor apparatuses generally including MOStransistors.

[0254] It is apparent from the above description including the examples,the MOS transistors disclosed herein are advantageous over previouslyknown similar devices and can be incorporated into various circuits andapparatuses.

[0255] As an example, the MOS transistor disclosed herein includes animpurity region for controlling narrow effect formed in the vicinity ofboth ends of a channel region in the direction of channel width, and ahigh concentration impurity region formed with an impurity concentrationapproximately equal to that of the channel stopper region at thelocation deeper than the channel stopper region.

[0256] The reverse narrow channel effect or the narrow channel effectcan therefore be controlled by suitably adjusting the impurityconcentration in the narrow effect controlling impurity region.

[0257] In the MOS transistor, another impurity region for controllingnarrow effect is formed preferably having the same kind, and the sameconcentration, of impurities as those of the impurity region forcontrolling narrow effect, in the region for forming another MOStransistor of a second conductivity type (opposite to that of the firstconductivity type) in the vicinity of both ends of a channel region inthe direction of channel width.

[0258] As a result, in the case where both NMOS and PMOS transistors areincluded, a first narrow effect controlling impurity region for the NMOSor PMOS transistor, and another narrow effect controlling impurityregion for the PMOS or NMOS transistor, can be formed simultaneously.Therefore, the number of steps of device production decreases and theproduction costs can be reduced.

[0259] In addition, since the impurities in the impurity region forcontrolling the narrow effect may have the conductivity type opposite tothat of the high concentration impurity region, proper control of thereverse narrow channel effect or narrow channel effect becomes feasiblefor depletion-mode NMOS transistors by implanting impurity ions of theconductivity type opposite to that of ions of the channel stopper.

[0260] In another aspect, a further semiconductor apparatus is providedincluding a current mirror circuit which incorporate MOS transistorsdisclosed herein. Since the MOS transistors disclosed herein isincorporated into the current mirror circuit, the precision in poweroutput for the current mirror circuit can be improved.

[0261] In addition, in a further semiconductor apparatus provided hereinincluding an analog circuit consisting dividing resistors for dividing avoltage to be measured and supplying a divided voltage, a referencevoltage source for supplying a reference voltage, and an operationalamplifier for comparing the divided voltage with reference voltage, theoperational amplifier is formed to include the above noted currentmirror circuit.

[0262] Since the analog circuit is formed including the abovementionedcurrent mirror circuit, the precision in power output thereof can beimproved.

[0263] A method is provided herein including the steps of (A) forming anoxidation resistant coating for defining the region for forming thefield oxide layer; (B) implanting ions of a first impurity forcontrolling reverse narrow channel effect into the semiconductorsubstrate using the oxidation resistant coating as a mask, as a firstimplantation process; (C) selectively forming a field oxide layerthrough heat treatment on the surface of the semiconductor substrate;and (D) implanting ions of a second impurity from above the field oxidelayer into the semiconductor substrate for forming a channel stopperregion at the location deeper than the first impurity channel stopperregion at least in the vicinity of both ends of the channel region inthe direction of channel width of the MOS transistor, as a secondimplantation process.

[0264] Therefore, the noted MOS transistor can be formed properly.

[0265] In addition, the present method for manufacturing the notedsemiconductor apparatus may alternatively be carried including the stepof, prior to the first implantation process (A), forming a well regionof a first conductivity type and a further well region of a secondconductivity type opposite to that of the first conductivity type; inwhich the first implantation process (B) is implemented such that theions of the first conductivity type are implanted, as the ions of thefirst impurity, into the well region of the first conductivity type andthe further well region of the second conductivity type; and which thesecond implantation process (D) is implemented with a mask patterncovering the region of the further well region of the secondconductivity type such that the ions of the first conductivity type areimplanted as the ions of the second impurity into the well region of thefirst conductivity type.

[0266] As a result, in the case where both NMOS and PMOS transistors areincluded, the number of steps of device production decreases and theproduction costs can be reduced.

[0267] A further method is herein provided including the steps of (A)forming a field oxide layer selectively through heat treatment on thesurface of the semiconductor substrate, (B) forming a mask patternhaving openings over the regions for forming a narrow effect controllingimpurity region and the channel stopper region, and subsequentlyimplanting ions of a first impurity for controlling the reverse narrowchannel effect into the semiconductor substrate using the mask patternas a mask, as a first implantation process, and (C) implanting ions of asecond impurity into the semiconductor substrate using the same maskpattern for forming a channel stopper region at the location deeper thanthe first impurity channel stopper region at least in the vicinity ofboth ends of the channel region in the direction of channel width of theMOS transistor, as a second implantation process.

[0268] Since the same mask pattern is used for the ion implantationprocesses, production costs can be reduced.

[0269] In addition, during the above noted methods the ions of the firstimpurity used in the first implantation process may have a conductivitytype opposite to that of the second impurity used in the secondimplantation process.

[0270] As a result, the methods for manufacturing a semiconductor devicedisclosed may also be adapted to depletion-mode NMOS transistors byimplanting impurity ions of the conductivity type opposite to that ofions of the channel stopper, whereby the reverse narrow channel effector narrow channel effect can properly be suppressed.

[0271] The process steps set forth in the present description on thefabrication of MOS transistors and semiconductor apparatusesincorporating the transistors may be implemented using conventionalgeneral purpose microprocessors, programmed according to the teachingsin the present specification, as will be appreciated to those skilled inthe relevant arts. Appropriate software coding can readily be preparedby skilled programmers based on the teachings of the present disclosure,as will also be apparent to those skilled in the relevant arts.

[0272] The present specification thus include also a computer-basedproduct which may be hosted on a storage medium, and includeinstructions which can be used to program a microprocessor to perform aprocess in accordance with the present disclosure. This storage mediumcan include, but not limited to, any type of disc including floppydiscs, optical discs, CD-ROMs, magneto-optical discs, ROMs, RAMs,EPROMs, EEPROMs, flash memory, magnetic or optical cards, or any type ofmedia suitable for storing electronic instructions.

[0273] Additional modifications and variations of the present inventionare possible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims, the inventionmay be practiced other than as specifically described herein.

What is claimed as new and desired to be secured by letters patent ofthe united states is:
 1. A semiconductor apparatus, comprising: a fieldoxide layer for device isolation formed on a semiconductor substrate; achannel stopper region formed under said field oxide layer; and a MOStransistor of a first conductivity type electrically isolated by saidfield oxide layer and said channel stopper region; said MOS transistorcomprising an impurity region for controlling a narrow channel effectformed in a vicinity of both ends of a channel region in a direction ofchannel width; and a high concentration impurity region formed having animpurity concentration approximately equal to that of said channelstopper region at a location deeper than said channel stopper region. 2.The semiconductor apparatus according to claim 1, further comprising: afurther impurity region for controlling a narrow channel effect formedhaving a same kind, and a same concentration, of impurities as those ofsaid impurity region for controlling said narrow channel effect, in aregion for forming a further MOS transistor of a second conductivitytype opposite to that of said first conductivity type in a vicinity ofboth ends of a channel region in a direction of channel width.
 3. Thesemiconductor apparatus according to claim 1, wherein: said impuritiesin said impurity region for controlling said narrow channel effect havea conductivity type opposite to that of said high concentration impurityregion.
 4. A semiconductor apparatus comprising a current mirrorcircuit, said current mirror circuit including at least a MOS transistorrecited in anyone of claims 1, 2 and
 3. 5. A semiconductor apparatus,comprising: an analog circuit including at least dividing resistors fordividing a voltage to be measured and supplying a divided voltage, areference voltage source for supplying a reference voltage, and anoperational amplifier for comparing said divided voltage with saidreference voltage, wherein: said operational amplifier includes at leastsaid current mirror circuit of claim
 4. 6. A method for manufacturing asemiconductor apparatus, said semiconductor apparatus including at leasta field oxide layer for device isolation formed on a semiconductorsubstrate; a channel stopper region formed under said field oxide layer;and a MOS transistor of a first conductivity type electrically isolatedby said field oxide layer and said channel stopper region; comprisingthe steps of: (A) forming an oxidation resistant coating for defining aregion for forming said field oxide layer; (B) implanting ions of afirst impurity for controlling a reverse narrow channel effect into saidsemiconductor substrate using said oxidation resistant coating as amask, as a first implantation process; (C) selectively forming a fieldoxide layer through heat treatment on a surface of said semiconductorsubstrate; and (D) implanting ions of a second impurity from above saidfield oxide layer into said semiconductor substrate for forming achannel stopper region at a location deeper than said first impuritychannel stopper region at least in a vicinity of both ends of saidchannel region in a direction of channel width of said MOS transistor,as a second implantation process.
 7. The method for manufacturing asemiconductor apparatus according to claim 6, further comprising thestep of: prior to said first implantation process (A), forming a wellregion of a first conductivity type and a further well region of asecond conductivity type opposite to that of said first conductivitytype; wherein: said first implantation process (B) is implemented suchthat said ions of said first conductivity type are implanted, as saidions of said first impurity, into said well region of said firstconductivity type and said further well region of said secondconductivity type; and said second implantation process (D) isimplemented with a mask pattern covering a region of said further wellregion of said second conductivity type such that said ions of saidfirst conductivity type are implanted as said ions of said secondimpurity into said well region of said first conductivity type.
 8. Themethod for manufacturing a semiconductor apparatus according to claim 6,wherein: said ions of said first impurity used in said firstimplantation process have a conductivity type opposite to that of saidions of said second impurity used in said second implantation process.9. A method for manufacturing a semiconductor apparatus, saidsemiconductor apparatus including at least a field oxide layer fordevice isolation formed on a semiconductor substrate; a channel stopperregion formed under said field oxide layer; and a MOS transistor of afirst conductivity type electrically isolated by said field oxide layerand said channel stopper region; comprising the steps of: (A) forming anoxidation resistant coating for defining a region for forming said fieldoxide layer and subsequently a field oxide layer selectively throughheat treatment on a surface of said semiconductor substrate; (B) forminga mask pattern having openings over regions for forming a narrow effectcontrolling impurity region and said channel stopper region, andsubsequently implanting ions of a first impurity for controlling areverse narrow channel effect into said semiconductor substrate usingsaid mask pattern as a mask, as a first implantation process; and (C)implanting ions of a second impurity into said semiconductor substrateusing said mask pattern as a mask for forming a channel stopper regionat a location deeper than said first impurity channel stopper region atleast in a vicinity of both ends of said channel region in a directionof channel width of said MOS transistor, as a second implantationprocess.
 10. The method for manufacturing a semiconductor apparatusaccording to claim 9, wherein: said ions of said first impurity used insaid first implantation process have a conductivity type opposite tothat of said ions of said second impurity used in said secondimplantation process.
 11. A semiconductor apparatus comprising currentmirror circuit means, said current mirror circuit means including atleast a MOS transistor recited in anyone of claims 1, 2 and
 3. 12. Asemiconductor apparatus, comprising: analog circuit means including atleast dividing resistor means for dividing a voltage to be measured andsupplying a divided voltage, reference voltage source means forsupplying a reference voltage, and operational amplifier means forcomparing said divided voltage with said reference voltage, wherein:said operational amplifier means includes at least said current mirrorcircuit means of claim 11.